1. Technical Field
The present invention relates to a device structure of a MOSFET having excellent high-frequency characteristics.
2. Related Art
In recent years, the mobile communication market has been expanding due to increasing demand, system sophistication, and widened applicability of mobile communication technology, and it is estimated that the market size of mobile communication services and appliances can reach 11 trillion yen in 2010. Accordingly, great expectation is put on transistors and ICs capable of handling frequency bands in the GHz region, which is suitable for use in communication appliances, mobile radio base stations, satellite communication, broadcast stations, and the like. Conventionally, as high-frequency analog devices handling these objects, GaAs ICs, silicon bipolar transistors, and BiCMOS LSIs have been mainly used.
However, in the mobile communication, in view of achieving low-price and low power consumption demanded by users or achieving a system downsized by a one-chip analog-digital hybrid LSI, there have been increasing market demands on high-performance, high-frequency LSIs provided by a CMOS.
A MOSFET in terms of a high-frequency analog silicon device, when compared with a bipolar transistor (hereinafter referred to as BJT), has the following characteristics.
(1) Possible High Integration
Compared to the BJT, the MOSFET can be subjected to microfabrication and occupies a smaller area on the chip.
(2) Low Distortion Characteristic
The current-voltage characteristic of the BJT is an exponential characteristic while that of the MOSFET is a square-law characteristic. Thus, adjacent higher harmonics 2f1±f2 and 2f2±f1 do not appear.
(3) High Gain and High Efficiency
Optimization of dimensions (gate width and gate length) of the MOSFET provides high gain and high efficiency. This can reduce the number of module stages, thus permitting a reduction in size and price of the LSI.
Next, performance requirements imposed on the high-frequency silicon MOSFET will be described.
(1) Improvement in Transconductance gm
To apply the MOSFET to a high-frequency LSI circuit, large transconductance gm needs to be provided for high gain.
A drain current Id of the MOSFET can be expressed by the following formula:Id=½*W/L×μn×Cox×(Vgs−Vt)2  (1).
Thus, the transconductance gm can be expressed as follows:gm=dI/dV=(2μn×Cox×Id×W/L)0.5  (2).
Here, μn represents electron mobility, Cox represents the gate oxide film capacity per unit area, and W and L represent the gate width and the gate length, respectively. When the current is fixed, the W/L ratio needs to be increased to increase the transconductance gm.
(2) Improvement in a Cutoff Frequency fT
The cutoff frequency fT represents a frequency at which the current gain is 1, and one of indexes expressing high frequency characteristics of the device. This requires a margin of approximately ten times the operating frequency.
The cutoff frequency fT of the FET can be expressed by formula below:fT=gm/2π(Cgs+Cdg)  (3).
The cutoff frequency fT is proportional to the transconductance gm and inversely proportional to the sum of the gate-source capacity Cgs and the drain-gate capacity Cdg.
Miniaturization of the gate length L permits achieving equivalent performance with a smaller gate width W, thus leading to system downsizing and cost reduction.
(3) Noise Reduction
To apply the MOSFET to a high-frequency LSI, it is required to reduce noise of the FET itself so that a faint input signal is not buried in noise.
Minimum noise figure NFmin in a region where the sum of gate resistance Rg and source resistance Rs (Rg+Rs) is large can be approximately expressed by formula below:NFmin=1+2πfKCgs√{square root over ( )}(Rg+Rs)/gm  (4).
This formula is known as Fukui formula, where K is a constant number.
This formula proves that a transistor with larger transconductance gm, smaller gate resistance Rg, and smaller source resistance Rs has lower noise.
(4) Improvement in a Maximum Oscillation Frequency
The maximum oscillation frequency fmax is a frequency at which power gain is 0, and can be expressed as in formula (5):fmax=fT/2√{square root over ( )}(Rg(1/W)×(Rds×2πfT×Cgd+Cgs(Ri+Rs))  (5).
As can be seen from the formula (5), the maximum oscillation frequency fmax is larger with smaller gate resistance Rg and smaller source resistance Rs. Although not expressed in the formula (5), it is also known that the maximum oscillation frequency fmax is larger with smaller source inductance Ls.
In a conventional high-frequency LSI, for the purpose of improving these high frequency characteristics, a salicide process capable of simultaneously making the resistance of the gate, source, and drain low, or a polycide process of making the resistance of only the gate electrode low has been applied to a conventional finger-type transistor. In future, a metal gate or the like will also be applied.
As has been described hereinbefore, it can be understood that the performance of the MOSFET in high-frequency applications is greatly dependent on device parasitic components such as the gate resistance, source resistance, gate and drain capacities, and the like. To achieve reduction in these parasitic components, work has been done on the layout structure.
Among these, as a MOSFET for achieving in particular a low noise figure and a high maximum oscillation frequency and also achieving higher function and lower cost of a high-frequency LSI applied to a mobile communication appliance or the like, there is proposed “a structure in which unit cells symmetrical about a center point thereof and each having a ring-shaped gate electrode are arranged in an array” by patent document 1 (Japanese Patent Application Laid-open No. 3276325) and non-patent document 1 (Symposium on VLSI Technology held on June 1997, “A Mesh-Arrayed MOSFET (MA-MOS) for High-frequency analog Applications” (by Hiroshi Shimomura, et al.)), and further non-patent document 2 (Symposium on VLSI Circuits held on June 1998, “A 9 mW 900 MHz CMOS LNA with mesh arrayed MOSFETs” (by Joji Hayashi, et al.)). This structure is meeting with reports proving the validity thereof at international conferences and the like, where the structure is referred to as “Mesh-Arrayed MOSFET (MA-MOS)”. FIG. 18 shows a structure in which a ring-shaped gate electrode included in a unit cell is octagon-shaped. FIG. 19 shows a structure in which a ring-shaped gate electrode included in a unit cell is quadrangle-shaped.
Patent document 2 (U.S. Pat. No. 6,601,224) and patent document 3 (U.S. Pat. No. 6,893,925) disclose technology of constructing a transistor by arranging a plurality of linear electrical conductors of a predetermined width serving as gate electrodes in the lateral direction and longitudinal direction, also forming a source region or a drain region in a region surrounded by these liner electrical conductors, and further rendering an inactive region each inter portion of the linear electrical conductors, which are arranged in the lateral direction and the longitudinal direction. As a result, the transistor achieved by this technology is configured to have a plurality of quadrangular ring-shaped gate electrodes provided in the lateral direction and the longitudinal direction.
In the transistor having the ring-shaped gate electrode structured as described above, when a unit transistor (unit cell) is formed with one ring-shaped gate electrode and a source region and a drain region respectively located inside and outside the ring-shaped gate electrode, forming a gate contact region for connecting a wire to the ring-shaped gate electrode described above and connecting together this gate contact region and the ring-shaped gate electrode described above with the gate drawing wire for each unit transistor can stabilize a voltage applied to the ring-shaped gate electrode or the like.
However, the transistors disclosed in patent document 1 and non-patent documents 1 and 2 described above suffer from the following drawbacks as shown in FIGS. 18 to 21. Hereinafter, these drawbacks will be described. FIGS. 18 to 21, in which a region inside the rectangular or octagonal ring-shaped gate electrode 1 is provided as, for example, a drain region 2, a region outside thereof is provided as, for example, a source region 3, two or four gate contact regions 6 are provided, and these gate contact regions 6 and the ring-shaped gate electrode 1 are connected together with gate drawing wires 5, clearly prove that the gate drawing wires 5 cross the active region 3 in any of the layouts. Consequently, unnecessary gate capacities Cgd and Cgs are added, which presents the drawback of inhibiting an improvement in the high frequency characteristics, such as noise and the maximum oscillation frequency in particular, as indicated in the formulae (4) and (5) provided for “performance requirements imposed on the high-frequency silicon MOSFET” described above.
The presence of a portion of the gate drawing wire 5 not drawn out, if any, results in the presence of a region where the gate electrode 1 is bent and a machining shape of the gate at this portion becomes unstable, thus presenting the drawback that a MOSFET with little characteristic variation cannot be provided.
On the other hand, patent documents 2 and 3 do not at all disclose that gate contact regions and gate drawing wires are provided on an individual unit transistor basis.